VLSI - 3

So continuing on the previous post of two current sources in series, this example is important when you analyze lot of circuits.

Lets assume you simulate with ideal current sources

Case 1 : When top current source > lower current source

Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between increases.

The reason it increases is that top current source pumps in current but the down source only sinks lesser current, hence forth the rest of the current will charge up the cap at the node and hence forth increases the node potential.

Case 2 : When top current source < lower current source

Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between decreases.

The reason it increases is that top current source pumps in lesser current but the down source only sinks higher current, hence forth the rest of the current will be provided by the cap at the node and hence forth decreases the node potential.

Interested studentts should find time in simulating the circuit by replacing the current sources with NMOS and PMOS and understand what will happen.

This is an important step in understanding CMFB.

Reset basics

Purpose of reset: We see that almost every electronic device has a reset button. Your video game has a reset button that resets the game and your unsaved progress is lost. Your laptop's reset button reboots it. Have you ever wondered why a system (or specifically a chip) has a reset? Well, the simple purpose of resets is to provide a known initial state to the system to start with. Another reason is, when the system accidentally goes into some unknown state (there may be many reasons for this), the system always knows how to get out of this and go into a known state by asserting a reset signal. 

Reset design strategies: Defining a reset is one of the most important decisions that needs to be taken for the good health of design. In general, following things need to be kept in mind during deciding reset strategy:

• What flops to receive reset: One of the easiest and safest approaches is to enable all the flip-flops in the design with a reset. However, there may be a some registers, whose initial state will not have any impact on the design state. In other words, it might not matter if the register's output is '0' or '1' when design goes in reset state. Such registers can be kept non-resettable after an analysis. Let us elaborate with the help of an example. Figure 1 shows a part of an FSM wherein two registers are feeding an AND gate. In figure 1(a), we have decided to initialize both to '0' during reset (with an asynchronous reset, to be explained later). However, given this scenario, if one of the flip-flops is provided with an initial state of '0', the output of the other will be gated. So, we may omit reset on one of the flip-flops. Figure 1(b) shows that omission of reset on one of the flip-flops does not have any impact on state machine design.

We may not always encounter such scenarios. If, instead of AND gate, we had an OR gate, we would not have been able to keep one of the flip-flops uninitialized during reset. Figure 2 shows such an example. In figure 2(b), if we remove reset from second flip-flop, output of OR gate goes 'X'; thus, impacting the state machine.

Another popular scenario wherein we can skip a few registers from having a reset pin is shift registers. If the first stage of a shift register is you give more than one clock pulses when in reset state, subsequent stages will get reset. If you have four stages, you need to give at least three clock pulses while in reset. The same is shown in figure below.

• Synchronous vs asynchronous reset: There are two kinds of reset assertion/deassertion strategies - synchronous vs asynchronous reset. Although each of the two can be used to effective implementation of reset, each of these has its own advantages/disadvantages. Designer may decide upon the desired strategy by considering the pros and cons.
• Synchronous reset means that the reset will affect the state of the design only on the active edge of the clock.
• Asynchronous reset resets the design asynchronously. For this purpose, flip-flops have a special pin that resets the output to '0' or '1' based upon the need. 

Read Next: Synchronous and asynchronous resets

Also read:

• Interview questions related to reset design and reset timing