VLSI UNIVERSE
Interview Questions
Listing the posts that are relevant to interviews and most frequently asked questions. Please add your experiences
here
so that these can act as a reference for others. You can also ask your query in
design forum
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Setup time and hold time basics
Multicycle paths - the architectural perspective
Interesting design question - BCD multiply by 5 circuit
Latchup in CMOS devices
Engineering change order (ECO)
Clock latency
Spare cells
Interesting problem - latches in series
Comparison between array, linked list and vector
Concept of temperature inversion
Negative gate delay - is it possible
Our world - digital or analog
Binary multiplier
Lockup latch
Data-to-data checks
What is static timing analysis
Can a net have negative delay
Implement 3 and 4-variable functions using 8:1 mux
Analog to digital converter
Controllability and observability
What is logic built-in self test (LBIST)
Scan chains
Clock gating checks at a mux
On-Chip Variations
Can hold be frequency dependant?
How propagation of 'X' happens through different logic gates
Virtual clock
Binary to thermometer encoder
Bubble errors and bubble error correction
Multicycle paths handling in STA
Implementing logic functions using multiplexer
Concept of time borrowing in latches
Why is body connected to ground and not to respective sources in CMOS design
How will you model skew with the help of data checks
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