Clock gating checks

Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. And a number of control signals are there which control these clocks. These signals are behind switching on and off the design. Let us say, we have a simple design as shown in the figure below. Pin ‘SEL’ selects between two clocks. Also, ‘EN’ selects if clock will be propagating to the sub-design or not. Similarly, there are signals that decide what, when, where and how for propagation of clocks. Some of these controlling signals may be static while some of these might be dynamic. Even with all this, these signals should not play with waveform of the clock; i.e. these should not cause any glitch in clock path. There are both architectural as well as timing care-abouts that are to be taken care of while designing for signals toggling in clock paths. This scenario is widely known as ‘clock gating’. The timing checks that need to be modeled in timing constraints are known as ‘clock gating checks’.

Two clocks are going to a sub-part of design and are controlled by two signals. SEL is used to select which clock will propagate. Further, there is a signal EN which decides if selected clock will propagate or not
Figure 1: A simplest clocking structure
Definition of clock gating check: A clock gating check is a constraint, either applied or inferred automatically by tool, that ensures that the clock will propagate without any glitch through the gate.

Types of clock gating checks: Fundamentally, all clock gating checks can be categorized into two types:


AND type clock gating check: Let us say we have a 2-input AND gate in which one of the inputs has a clock and the other input has a data which will toggle while the clock is still on.

EN signal controlling CLK_in signal
Figure 2: AND type clock gating check; EN signal
controlling CLK_IN through AND gate
Since, the clock is free-running, we have to ensure that the change of state of enable signal does not cause the output of the AND gate to toggle. This is only possible if the enable input toggles when clock is at ‘0’ state. As is shown in figure 3 below, if ‘EN’ toggles when ‘CLK_IN’ is high, the clock pulse gets clipped. In other words, we do not get full duty cycle of the clock. Thus, this is a functional architectural miss causing glitch in clock path. As is evident in figure 4, if ‘EN’ changes during ‘CLK_IN’ are low, there is no change in clock duty cycle. Hence, this is the right way to gate a clock signal with an enable signal; i.e. make the enable toggle only when clock is low.

If the enable signal toggles when clock is high, the output clock from an AND gate will be glitchy
Figure 3: Clock being clipped when ‘EN’ changes when ‘CLK_IN’ is high

If enable signal toggles when clock is low, clock will pass without any glitch
Figure 4: Clock waveform not being altered when ‘EN’ changes when ‘CLK_IN’ is low


Theoretically, ‘EN’ can launch from either positive edge-triggered or negative edge-triggered flops. In case ‘EN’ is launched by a positive edge-triggered flop, the setup and hold checks will be as shown in figure 5. As shown, setup check in this case is on the next positive edge and hold check is on next negative edge. However, the ratio of maximum and minimum delays of cells in extreme operating conditions may be as high as 3. So, architecturally, this situation is not possible to guarantee the clock to pass under all conditions.


When enable signal is launched from a positive edge-triggered register/latch, hold check is on next negative edge, which cannot be met.
Figure 5: Clock gating setup and hold checks on AND gate when 'EN' launches from a positive edge-triggered flip-flop

On the contrary, if ‘EN’ launches from a negative edge-triggered flip-flop, setup check are formed with respect to the next rising edge and hold check is on the same falling edge (zero-cycle) as that of the launch edge. The same is shown in figure 6. Since, in this case, hold check is 0 cycle, both the checks are possible to be met for all operating conditions; hence, this solution will guarantee the clock to pass under all operating condition provided the setup check is met for worst case condition. The inactive clock state, as evident, in this case, is '0'.

When enable launches from negative-edge register/latch, hold check is zero cycle, which is possible to meet under all timing corners.
Figure 6: Clock gating setup and hold checks on AND gate when ‘EN’ launches from negative edge-triggered flip-flop


OR gate forming a clock gating check
Figure 7: An OR gate controlling a clock signal 'CLK_IN'
OR type clock gating check: Similarly, since the off-state of OR gate is 1, the enable for an OR type clock gating check can change only when the clock is at ‘1’ state. That is, we have to ensure that the change of state of enable signal does not cause the output of the OR gate to toggle. Figure 9 below shows if ‘EN’ toggles when ‘CLK_IN’ is high, there is no change in duty cycle. However, if ‘EN’ toggles when ‘CLK_IN’ is low (figure 8), the clock pulse gets clipped. Thus, ‘EN’ must be allowed to toggle only when ‘CLK_IN’ is high.


If the enable signal toggles when clock is low, the output clock from an OR gate will be glitchy
Figure 8: Clock being clipped when 'EN' changes when 'CLK_IN' is low

If enable signal toggles when clock is high, clock will pass without any glitch
Figure 9: Clock waveform not being altered when 'EN' changes when 'CLK_IN' is low


As in case of AND gate, here also, ‘EN’ can launch from either positive or negative edge flops. In case ‘EN’ launches from negative edge-triggered flop, the setup and hold checks will be as shown in the figure 10. The setup check is on the next negative edge and hold check is on the next positive edge. As discussed earlier, it cannot guarantee the glitch less propagation of clock.

When enable signal is launched from a negative register/latch, hold check is on next positive edge, which cannot be met.
Figure 10: Clock gating setup and hold checks on OR gate when ‘EN’ launches from negative edge-triggered flip-flop

If ‘EN’ launches from a positive edge-triggered flip-flop, setup check is with respect to next falling edge and hold check is on the same rising edge as that of the launch edge. The same is shown in figure 11. Since, the hold check is 0 cycle, both setup and hold checks are guaranteed to be met under all operating conditions provided the path has been optimized to meet setup check for worst case condition. The inactive clock state, evidently, in this case, is '1'.
When enable launches from positive-edge register/latch, hold check is zero cycle, which is possible to meet under all timing corners.
Figure 11: Clock gating setup and hold checks on OR gate when 'EN' launches from a positive edge-triggered flip-flop

We have, thus far, discussed two fundamental types of clock gating checks. There may be complex combinational cells other than 2-input AND or OR gates. However, for these cells, too, the checks we have to meet between the clock and enable pins will be of the above two types only. If the enable can change during low phase of the clock only, it is said to be AND type clock gating check and vice-versa.

SDC command for application of clock gating checks: In STA, clock gating checks can be applied with the help of SDC command set_clock_gating_check.

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15 comments:

  1. Hi .. The sequential element in Fig 5 and Fig 6 must be positive latch and negative latch instead of FF's right?

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    1. Hi.. I can sense where the query is coming from. Basically, a negative FF is a positive latch followed by a negative latch. So, the basic structure remains same with positive latch in negative FF becoming redundant in this case, if the signal do negative FF is coming from a positive FF. Also here we are just talking about discrete AND/OR as clock gating elements, and not ICGs. But in this discussion also, we can replace FFs with corresponding latch. I hope I was able to answer your query.

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  2. how can we approach to fix setup for paths as shown in fig 6? Thank you in advance.

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    1. Hi

      All the basic setup fixing techniques will help here, which are listed here:

      https://vlsiuniverse.blogspot.com/2017/10/improving-duty-cycle-of-clock.html

      Other than these, since, the setup check here is half cycle check, you can try to make negative pulse wider too. :-)

      https://vlsiuniverse.blogspot.com/2017/10/improving-duty-cycle-of-clock.html

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  3. Please edit the contents as there are minor mistakes. Figure 8 and 9 doesn't make sense with respect to the comments specified.

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    1. Hi

      Corrected the type. Thanks for your valuable input.

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  4. the heading of figure 9 still looks wrong. The caption should be 'EN' changes when 'CLK_IN' is high

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  5. Why are these waveforms different from the ones here: https://vlsiuniverse.blogspot.com/2013/08/setup-and-hold-checks-part-ii-static.html? Shouldn't the posedge flop to AND gate path waveform be same as pos edge flop to pos edge latch? Also, how is a clocked AND gate different from the pos edge latch?

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    1. Hi

      Very good question. And I must say you completely understand the concepts. I wrote this post when my understanding was limited, and I owe to update this post now with relevant information. Now, coming to your question, you are very right in saying so, but there is a slight twist that our state machines must be consistent with the setup/hold checks that we are following.

      In case of a pos-flop -> AND gate, the setup/hold checks of a latch will work perfectly as far as timing is concerned, but you need to make an FSM that confirms to same. The default behavior of AND clock gating from pos flop is the one shown in this post.

      This is due to the default behavior and widely accepted understanding of setup/hold checks.

      Let us try to understand default behavior of setup/hold checks. Let us say, data is launched at time T. Now, the next instant data can be captured in a positive latch is T+, whereas in an AND gate (assuming perfect transitions), it is T+full_cycle. This is why, the default behavior is different for both.

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  6. Hi Can you please explain why during positive flop and and gate hold check is done on the negative edge and also in or case and negative flop?

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    1. Hi

      Launch flip-flop does not have anything to do with it. In case of AND gate, you need enable to toggle during clock low, so negative edge forms hold check and positive edge forms setup check. Vice-versa in case of an OR Gate.

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  7. you wrote " Figure 9 below shows if ‘EN’ toggles when ‘CLK_IN’ is high, there is no change in duty cycle." but there is change in the duty cycle!
    the clk_out duty cycle is not as clk duty cycle, can you explain it please?

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  8. Can you elaborate more on Fig.6? I still don't get why hold/setup check. Next stage FF is omitted right? Plus, specify two waveforms in Fig 6 please. Thanks in advance.

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  9. As now a days we are using ICG, do we still need to check setup and hold in the above mentioned way?

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    Replies
    1. mostly not, but you never know what kind of design you find being implemented.

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