Setup checks and hold checks for latch-to-reg timing paths

There can be 4 cases of latch-to-register timing paths as discussed below:
1. Positive level-sensitive latch to positive edge-triggered register: Figure 1 below shows a timing path being launched from a positive level-sensitive latch and being captured at a positive edge-triggered register. In this case, setup check will be full cycle with zero-cycle hold check. Time borrowed by previous stage will be subtracted from the present stage.
Timing path from a positive level-sensitive latch to a positive edge-triggered register
Figure 1: Positive level-sensitive latch to positive edge-triggered register timing path
Timing waveforms corresponding to setup check and hold check for a timing path from positive level-sensitive latch to positive edge-triggered register is as shown in figure 2 below.
Setup and hold checks for timing path from positive level sensitive latch to positive edge triggered register
Figure 2: Setup and hold check waveform for positive latch to positive register timing path
2. Positive level-sensitive latch to negative edge-triggered register: Figure 3 below shows a timing path from a positive level-sensitive latch to negative edge-triggered register. In this case, setup check will be half cycle with half cycle hold check. Time borrowed by previous stage will be subtracted from the present stage.

Timing path from positive level sensitive latch to negative edge triggered register
Figure 3: A timing path from positive level-sensitive latch to negative edge-triggered register
Timing waveforms corresponding to setup check and hold check for timing path starting from positive level-sensitive latch and ending at negative edge-triggered register is shown in figure 4 below:
Timing waveforms corresponding to timing from positive level sensitive latch to negative edge triggered flip-flop
Figure 4: Setup and hold check waveform for timing path from positive latch to negative register


3. Negative level-sensitive latch to positive edge-triggered register: Figure 5 below shows a timing path from a negative level-sensitive latch to positive edge-triggered register. Setup check, in this case, as in case 2, is half cycle with half cycle hold check. Time borrowed by previous stage will be subtracted from the present stage.

Timing path from negative level sensitive latch to positve edge triggered flop
Figure 5: Timing path from negative level-sensitive latch to positive edge-triggered register
Timing waveforms for path from negative level-sensitive latch to positive edge-triggered flop are shown in figure 6 below:
Timing waveform for timing path from negative level sensitive latch to negative edge triggered register
Figure 6: Waveform for setup check and hold check corresponding to timing path from negative latch to positive flop

4. Negative level-sensitive latch to negative edge-triggered register: Figure 7 below shows a timing path from negative level-sensitive latch from a negative edge-triggered register. In this case, setup check will be single cycle with zero cycle hold check. Time borrowed by previous stage will be subtracted from present stage.

Timing path from negative level sensitive latch to negative edge triggered register
Figure 7: Timing path from negative latch to negative flop
Figure 8 below shows the setup check and hold check waveform from negative level-sensitive latch to negative edge-triggered flop.

Timing waveform for timing path strating from negative level sensitive latch and ending at negative edge-triggered register
Figure 8: Timing waveform for path from negative latch to negative flip-flop




16x1 mux using 4x1 muxes

Implementing 16:1 multiplexer with 4:1 multiplexers: A 16x1 mux can be implemented using 5 4x1 muxes. 4 of these multiplexers can be used as first stage to mux 4 inputs each with two least significant bits of select lines (S0 and S1), resulting in 4 intermediate outputs, which, then can be muxed again using a 4:1 mux. The implementation of 16x1 mux using 4x1 muxes is shown below in figure 1:

A 16-input mux can be made from 5 4-inputs muxes.
Implementing 16:1 mux with the help of 4:1 multiplexers