Following strategies can be useful in reducing the magnitude of hold violation and bringing the slack towards a positive value:
1. Insert delay elements: The increase in data path delay can be increased if we insert delay elements in the data-path. Thus, the hold violating path's delay can be increased, and hence, slack can be made positive by inserting buffers in hold violating data-path.
2. Reduce the drive strength of data-path logic gates: Replacing a cell with a similar cell of less drive strength will certainly add delay to data-path. However, there is a slight chance of decrease in data-path delay if the cell load is dominated by intrinsic capacitance as we discussed in xkfjjkdsf
3. Use data-path cells with higher threshold voltages: If you have multiple flavors of threshold voltages in your design, the cells with higher threshold voltage will certainly have higher delays. So, this must be the first option you must be looking for to resolve hold violations.
4. Improve hold time of capturing flip-flop: Using a capturing flip-flop with higher drive strength and/or lower threshold voltage will give a lower hold time requirement. Also, degrading the transition at flip-flop's clock pin reduces its hold time requirement.
5. Detoured routing: Detoured routing can be adoped as an alternative to insertion of delay elements as it will add load to the driving cell as well as provide additional net delay thereby increasing the data-path delay.
6. Play with clock skew: A positive skew degrades hold timing and a negative skew aids hold timing. So, if a data-path is violating, we can either decrease the latency of capturing flip-flop or increase the clock latency of launching flip-flop. However, in doing so, we need to keep in mind the setup and hold slacks of other timing paths starting and/or ending at these flip-flops.
7. Increase the clk->q delay of launching flip-flop: A launching flip-flop with more clk->q delay will help ease the hold timing of the data-path. For this, either we can decrease the drive strength of the flip-flop or move it to higher threshold voltage.